Understanding Circuits & Gates

intermediate8 min

What Is a Circuit?

In Minerva, a circuit is a directed acyclic graph of arithmetic operations. Each operation is a gate that takes inputs and produces outputs. Together, the gates encode a claim you want to prove.

Gate Types

Minerva supports these gate types:

Gate	Operation	Example
`add`	Addition	`add(a, b) → a + b`
`mul`	Multiplication	`mul(a, b) → a × b`
`gt`	Greater-than	`gt(a, b) → 1 if a > b, else 0`
`eq`	Equality	`eq(a, b) → 1 if a = b, else 0`
`range`	Range check	`range(x, min, max) → 1 if min ≤ x ≤ max`
`hash_eq`	Hash equality	`hash_eq(data, hash) → 1 if hash(data) = hash`

Circuit Structure

A circuit definition in Minerva looks like this:

{
  "name": "Revenue Range Proof",
  "inputs": {
    "public": ["min_revenue", "max_revenue"],
    "private": ["actual_revenue"]
  },
  "gates": [
    { "type": "gt", "inputs": ["actual_revenue", "min_revenue"], "output": "above_min" },
    { "type": "gt", "inputs": ["max_revenue", "actual_revenue"], "output": "below_max" },
    { "type": "mul", "inputs": ["above_min", "below_max"], "output": "in_range" }
  ],
  "outputs": ["in_range"]
}

How Gates Become Constraints

Each gate translates into polynomial constraints over a finite field. The STARK prover must satisfy all constraints simultaneously.

For example, the `gt(a, b)` gate becomes:

•Compute `diff = a - b`

•Prove `diff` is positive (range check over the field)

•Output 1 if positive, 0 otherwise

Composing Gates

Gates can be chained. The output of one gate feeds into the input of another:

gt(revenue, min) → above_min
gt(max, revenue) → below_max  
mul(above_min, below_max) → in_range

The `mul` gate here acts as a logical AND — both conditions must be true (1 × 1 = 1).

Public vs. Private Inputs

Designing with Juno

Don't want to write circuit JSON by hand? Ask Juno to design one:

"I need to prove my company's quarterly emissions are between 500 and 2000 tonnes CO2 without revealing the exact number"

Juno will generate the circuit definition, explain each gate, and let you review before proving.

Limitations

•Circuit complexity increases proof generation time roughly linearly

← More guides